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trigger [2015/10/20 12:48] pereira [Scalers and dead time] |
trigger [2017/09/09 17:07] pereira [Inputs and outputs] |
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==== Inspect channels ==== | ==== Inspect channels ==== | ||
- | A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | + | A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI by right clicking on the corresponding drawn " |
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^ A4 (in) | External 2 source ^ B4 (out) | QDC gate ^ C4 (in) | Busy 4 ^ D4 (out) | External 2 source | | ^ A4 (in) | External 2 source ^ B4 (out) | QDC gate ^ C4 (in) | Busy 4 ^ D4 (out) | External 2 source | | ||
^ A5 (in) | Clear busy ^ B5 (out) | TDC start ^ C5 (in) | Busy 5 ^ D5 (out) | S800 trigger | | ^ A5 (in) | Clear busy ^ B5 (out) | TDC start ^ C5 (in) | Busy 5 ^ D5 (out) | S800 trigger | | ||
- | ^ A6 (in) | Clear module | + | ^ A6 (in) | Clear module |
^ A7 (in) | Gretina sync ^ B7 (out) | ^ C7 (in) | Busy 7 ^ D7 (out) | External 1 trigger | | ^ A7 (in) | Gretina sync ^ B7 (out) | ^ C7 (in) | Busy 7 ^ D7 (out) | External 1 trigger | | ||
^ A8 (in) | Time stamp clock ^ B8 (out) | Live trigger | ^ A8 (in) | Time stamp clock ^ B8 (out) | Live trigger | ||
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====== Time stamping ====== | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | + | The S800 ULM trigger |
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | + | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: |
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- | + | ||
- | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: | + | |
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====== Configuration for S800 in tandem with other detectors ====== | ====== Configuration for S800 in tandem with other detectors ====== | ||
- | In its standard configuration, | + | In its standard configuration, |
To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | ||
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====== Begin sequence ====== | ====== Begin sequence ====== | ||
+ | OBSOLETE: THIS SECTION IS BEING UPDATED | ||
+ | |||
The internal " | The internal " | ||