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trigger [2015/10/30 16:08]
pereira [Time stamping]
trigger [2017/09/09 17:07] (current)
pereira [Inputs and outputs]
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 ==== Inspect channels ==== ==== Inspect channels ====
-A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. ​+A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI by right clicking on the corresponding drawn "​wire"​, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. ​
  
  
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 ^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source | ^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source |
 ^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger | ^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger |
-^ A6 (in) | Clear module ​     ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6           ​^ D6 (out)  | Coincidence trigger |+^ A6 (in) | Clear module ​     ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6   ​^ D6 (out)  | Coincidence trigger |
 ^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger | ^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger |
 ^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger ​         ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger| ^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger ​         ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger|
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 ====== Time stamping ====== ====== Time stamping ======
-The S800 ULM trigger module provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#​Trigger Schematics|GUI]]). The clock is inhibited by a "​Go"​ signal controlled by the trigger module. While "​Go"​ is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "​[[Trigger#​Begin sequence|Begin sequence]]"​). The clock signal is released when the "​Go"​ signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. ​+The S800 ULM trigger module provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used (as it is donefor instance, when running with GRETINA). The clock is inhibited by a "​Go"​ signal controlled by the trigger module. While "​Go"​ is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "​[[Trigger#​Begin sequence|Begin sequence]]"​). The clock signal is released when the "​Go"​ signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. ​
  
 The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:​wiki:​stamp64.pdf|here}}. The inputs are the following: ​ The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:​wiki:​stamp64.pdf|here}}. The inputs are the following: ​
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 ====== Configuration for S800 in tandem with other detectors ====== ====== Configuration for S800 in tandem with other detectors ======
-In its standard configuration,​ the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module. ​+In its standard configuration,​ the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 ([[Trigger#​Inputs and outputs|inputs C1 and C2]]) of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module. ​
 To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: ​ To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: ​
  
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 ====== Begin sequence ====== ====== Begin sequence ======
 +OBSOLETE: THIS SECTION IS BEING UPDATED
 +
 The internal "​Go"​ state of the trigger module is controlled via CAMAC commands. When "​Go"​ is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "​Go"​ state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. The internal "​Go"​ state of the trigger module is controlled via CAMAC commands. When "​Go"​ is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "​Go"​ state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
  
trigger.1446235689.txt.gz ยท Last modified: 2015/10/30 16:08 by pereira