S800 Documentation

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trigger [2016/03/16 15:03]
pereira [Configuration for S800 in tandem with other detectors] 		trigger [2023/10/24 16:47] (current)
swartzj [Trigger schematics]
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 ===== Trigger schematics ===== ===== Trigger schematics =====
    
-The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop.+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u4pc8]] desktop.
  
 {{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}} {{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
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 ==== Inspect channels ==== ==== Inspect channels ====
-A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. +A set of four inspect channels are patched out to the data-U4 panels. Each channel can be assigned to any connection drawn on the GUI by right clicking on the corresponding drawn "wire", thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. 
  
  
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 ^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source | ^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source |
 ^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger | ^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger |
-^ A6 (in) | Clear module      ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6           ^ D6 (out)  | Coincidence trigger |+^ A6 (in) | Clear module      ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6   ^ D6 (out)  | Coincidence trigger |
 ^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger | ^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger |
 ^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger          ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger| ^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger          ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger|
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 ====== Begin sequence ====== ====== Begin sequence ======
 +OBSOLETE: THIS SECTION IS BEING UPDATED
 +
 The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
  
trigger.1458154996.txt.gz ยท Last modified: 2016/03/16 15:03 by pereira

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