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— verilog_trigger [2013/12/11 15:50] (current)
pereira created
Line 1: Line 1:
 +Below is the Verilog code used in the configuration for the INTERNAL module:
 +
 +  module INTERNAL (N, S1, S2, Clock, F, A, Data_in, 
 +  DriveRead, Q, X, Data_out, 
 +  S800Delay, S800Width, 
 +  SecondaryDelay, SecondaryWidth, 
 +  S800TimingDelay, CoincTimingWidth,
 +  SecondaryTimingDelay, Bypasses,
 +  S800Factor, SecondaryFactor, TriggerBox,
 +  ADCGate, QDCGate, TDCStart, Coincidence,
 +  Inspect1, Inspect2, Inspect3, Inspect4,
 +  Register, ClearModule, ClearRegister, Go, 
 +  TimeStamp, Select, SyncEnable
 +  ) ;
 +  
 +  input N ;
 +  input S1 ;
 +  input S2 ;
 +  input Clock ;
 +  input [4:0] F ;
 +  input [3:0] A ;
 +  input [23:0] Data_in ;
 +  output Q ;
 +  output X ;
 +  output DriveRead;
 +  output [23:0] Data_out ;
 +  output [7:0] S800Delay;
 +  output [7:0] S800Width ;
 +  output [7:0] SecondaryDelay;
 +  output [7:0] SecondaryWidth ;
 +  output [7:0] S800TimingDelay;
 +  output [7:0] CoincTimingWidth ;
 +  output [7:0] SecondaryTimingDelay ;
 +  output [4:0] Bypasses ;
 +  output [9:0] S800Factor ;
 +  output [9:0] SecondaryFactor ;
 +  output [4:0] TriggerBox ;
 +  output [7:0] ADCGate ;
 +  output [7:0] QDCGate ;
 +  output [7:0] TDCStart ;
 +  output [7:0] Coincidence ;
 +  output [4:0] Inspect1 ;
 +  output [4:0] Inspect2 ;
 +  output [4:0] Inspect3 ;
 +  output [4:0] Inspect4 ;
 +  input [4:0] Register;
 +  output ClearModule;
 +  output ClearRegister;
 +  output Go;
 +  input [63:0] TimeStamp;
 +  output [1:0] Select;
 +  output SyncEnable;
 +  
 +  // add your declarations here
 +  reg X;
 +  reg Q;
 +  reg DriveRead ;
 +  reg ClearModule;
 +  reg ClearRegister;
 +  reg Go;
 +  reg [1:0] Select;
 +  reg SyncEnable;
 +  reg [23:0] Data_out ;
 +  reg [7:0] S800Delay;
 +  reg [7:0] S800Width ;
 +  reg [7:0] SecondaryDelay;
 +  reg [7:0] SecondaryWidth ;
 +  reg [7:0] S800TimingDelay;
 +  reg [7:0] CoincTimingWidth ;
 +  reg [7:0] SecondaryTimingDelay ;
 +  reg [4:0] Bypasses ;
 +  reg [9:0] S800Factor ;
 +  reg [9:0] SecondaryFactor ;
 +  reg [4:0] TriggerBox ;
 +  reg [7:0] ADCGate ;
 +  reg [7:0] QDCGate ;
 +  reg [7:0] TDCStart ;
 +  reg [7:0] Coincidence ;
 +  reg [4:0] Inspect1 ;
 +  reg [4:0] Inspect2 ;
 +  reg [4:0] Inspect3 ;
 +  reg [4:0] Inspect4 ;
 +  
 +  // add your code here
 +  always @(posedge Clock) begin
 +    if (N) begin
 +    case (F)
 +      5'd0: begin
 +      case (A)
 +        4'd0: Data_out <= {16'd0, S800Delay};
 +        4'd1: Data_out <= {16'd0, S800Width};
 +        4'd2: Data_out <= {16'd0, SecondaryDelay};
 +        4'd3: Data_out <= {16'd0, SecondaryWidth};
 +        4'd4: Data_out <= {16'd0, S800TimingDelay};
 +        4'd5: Data_out <= {16'd0, CoincTimingWidth};
 +        4'd6: Data_out <= {16'd0, SecondaryTimingDelay};
 +        4'd7: Data_out <= {19'd0, Bypasses};
 +        4'd8: Data_out <= {14'd0, S800Factor};
 +        4'd9: Data_out <= {14'd0, SecondaryFactor};
 +        4'd10: Data_out <= {19'd0, TriggerBox};
 +        4'd11: Data_out <= {23'd0, Go};
 +        4'd12: Data_out <= {22'd0, Select};
 +        4'd13: Data_out <= {23'd0, SyncEnable};
 +        4'd14: Data_out <= 24'd5800;
 +        4'd15: Data_out <= 24'd2367;
 +        default: Data_out <= 24'd0;
 +      endcase //A
 +      end // F=0
 +      
 +      5'd1: begin
 +      case (A)
 +        4'd0: Data_out <= {19'd0, Inspect1};
 +        4'd1: Data_out <= {19'd0, Inspect2};
 +        4'd2: Data_out <= {19'd0, Inspect3};
 +        4'd3: Data_out <= {19'd0, Inspect4};
 +        default: Data_out <= 24'd0;
 +      endcase //A
 +      end // F=1
 +      
 +      5'd2: begin
 +      case (A)
 +        4'd0: Data_out <= {16'd0, ADCGate};
 +        4'd1: Data_out <= {16'd0, QDCGate};
 +        4'd2: Data_out <= {16'd0, TDCStart};
 +        4'd3: Data_out <= {16'd0, Coincidence};
 +        default: Data_out <= 24'd0;
 +      endcase //A
 +      end // F=2
 +      
 +      5'd3: begin
 +      case (A)
 +        4'd0: Data_out <= {19'd0, Register};
 +        4'd1: Data_out <= {8'd0, TimeStamp[15:0]};
 +        4'd2: Data_out <= {8'd0, TimeStamp[31:16]};
 +        4'd3: Data_out <= {8'd0, TimeStamp[47:32]};
 +        4'd4: Data_out <= {8'd0, TimeStamp[63:48]};
 +        default: Data_out <= 24'd0;
 +      endcase //A
 +      end // F=3
 +      
 +      5'd9: begin
 +      end // F=9
 +  
 +      5'd16: begin
 +      if (S1) begin
 +        case (A)
 +        4'd0: S800Delay <= Data_in[7:0];
 +        4'd1: S800Width <= Data_in[7:0];
 +        4'd2: SecondaryDelay <= Data_in[7:0];
 +        4'd3: SecondaryWidth <= Data_in[7:0];
 +        4'd4: S800TimingDelay <= Data_in[7:0];
 +        4'd5: CoincTimingWidth <= Data_in[7:0];
 +        4'd6: SecondaryTimingDelay <= Data_in[7:0];
 +        4'd7: Bypasses <= Data_in[4:0];
 +        4'd8: S800Factor <= Data_in[9:0];
 +        4'd9: SecondaryFactor <= Data_in[9:0];
 +        4'd10: TriggerBox <= Data_in[4:0];
 +        4'd11: Go <= Data_in[0:0];
 +        4'd12: Select <= Data_in[1:0];
 +        4'd13: SyncEnable <= Data_in[0:0];
 +        endcase //A
 +      end // S1=1
 +      end // F=16
 +        
 +      5'd17: begin
 +      if (S1) begin
 +        case (A)
 +          4'd0: Inspect1 <= Data_in[4:0];
 +          4'd1: Inspect2 <= Data_in[4:0];
 +          4'd2: Inspect3 <= Data_in[4:0];
 +          4'd3: Inspect4 <= Data_in[4:0];
 +        endcase //A
 +      end // S1=1
 +      end // F=17
 +        
 +      5'd18: begin
 +      if (S1) begin
 +        case (A)
 +          4'd0: ADCGate <= Data_in[7:0];
 +          4'd1: QDCGate <= Data_in[7:0];
 +          4'd2: TDCStart <= Data_in[7:0];
 +          4'd3: Coincidence <= Data_in[7:0];
 +        endcase //A
 +      end // S1=1
 +      end // F=18
 +       
 +    endcase // F
 +    end //N=1
 +  
 +  end // always Clock
 +  
 +  always @(N or S1 or F or A) begin
 +    if (N) begin
 +    
 +    case (F)
 +    
 +    5'd0: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b1;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=0
 +  
 +    5'd1: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b1;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=1
 +  
 +    5'd2: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b1;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=2
 +  
 +    5'd3: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b1;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=3
 +  
 +    5'd9: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b0;
 +      ClearModule = 1'b1;
 +      ClearRegister = 1'b0;
 +    end // F=9
 +  
 +    5'd10: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b0;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b1;
 +    end // F=9
 +  
 +    5'd16: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b0;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=16
 +    
 +    5'd17: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b0;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=17
 +    
 +    5'd18: begin
 +      X = 1'b1;
 +      Q = 1'b1;
 +      DriveRead = 1'b0;
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +    end // F=18
 +    
 +    default: begin
 +      DriveRead = 1'b0; 
 +      ClearModule = 1'b0;
 +      ClearRegister = 1'b0;
 +      X = 1'b0;
 +      Q = 1'b0;
 +    end // default F
 +  
 +    endcase // F
 +    end // if (N)
 +    
 +    else begin
 +    DriveRead = 1'b0;
 +    ClearModule = 1'b0;
 +    ClearRegister = 1'b0;
 +    X = 1'b0;
 +    Q = 1'b0;
 +    end // if (!N)
 +  end // always N or S1 or A or F
 +  
 +  endmodule
 +
 +
 +
 +
 +
 +
  
verilog_trigger.txt ยท Last modified: 2013/12/11 15:50 by pereira

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