• Crate Configuration
• Inventory Modules
• Electronic Diagrams
• Trigger

A preliminary scheme of the crate configuration (in progress) can be found here.

In progress.

• Main Electronic Diagram
• CRDC Schematic Electronic Diagram
• Ion Chamber Schematic Electronics Diagram
• Tracking PPAC Schematic Electronics Diagram
• Trigger Schematic Electronics Diagram
• Fast Timing Schematic Electronics Diagram

The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator E1 and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.

This section is divided in the following subsections:

1. Ordered List ItemSchematics
2. - Ordered List ItemTrigger Box

• Busy Scheme
• Time stamping Scheme
• Gate Generation
• Inspect Channel

* Trigger Module

• CAMAC Commands
• Inputs and Outputs
• FPGA firmware

* Time Stamping Configuration for S800 in tandem with other detectors 4 Begin sequence 5 Scalers and dead time

The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:

1. Simplify cabling and setup of the trigger
2. Reduce the number of modules used to implement the trigger
3. Ability to remotely control and inspect trigger signals
4. Ability to save and restore the trigger configuration
5. Direct visualization of the trigger logic and configuration

Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors.

The S800 trigger from the E1 scintillator provides also the reference time for the CRDCs as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.

The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.

The two main trigger sources are labeled “S800” and “Secondary” in the GUI (the leftmost side of the layout). Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.

In addition to the singles and coincidence triggers, two separate trigger sources labeled “External 1” and “External 2” can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.

Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the “Raw trigger” output of the trigger box may generate two pulses for a single event. A scaler connected to the “Raw trigger” output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check section Scalers ). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp (check trigger packet tag 0x2367 in the DAQ section for more information).

More details about the trigger box module and its FPGA schematics can be found here.

All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated.

A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.

As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the “Raw trigger” signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the “Live trigger” signal stays true as long as the longest busy signal. The “Live trigger” signal is therefore a “global busy” signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the “Raw trigger” signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started.

Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.

The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a “Go” signal controlled by the trigger module. While “Go” is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on begin sequence). The clock signal is released when the “Go” signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.

The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [stamp64.pdf|here]]. The inputs are the following:

E1: time stamp clock input

E2: latch input

E3: clear input

The clear can be done via software as well, and is usually done that way.

Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:

In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module. To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: • Raw trigger from external detector to Secondary source • Live trigger from S800 trigger to external data acquisition (trigger input) • Time stamp clock from S800 trigger to external data acquisition (time stamp input) • End-of-event from external data acquisition to S800 trigger • Busy from external data acquisition to S800 trigger

Begin sequence

The internal “Go” state of the trigger module is controlled via CAMAC commands. When “Go” is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the “Go” state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.

The data acquisition begin sequence of the trigger module is the following: reset time stamp counter to 0 reset trigger register to 0 after all modules in all crates have been initialized, send CAMAC command to set “Go” state to true after a preset delay of 200 to 300 microseconds, the “Go” level is set to true

The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the “Go” state of the module back to false.

Scalers and dead time

The “D” connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping in the inputs and outputs section below). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, in addition to the information coded for each event in the trigger register.

In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.

Trigger module

The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section describes the functionality of the S800 trigger module and the commands used to control its parameters.

CAMAC commands

The following table lists the CAMAC codes recognized by the trigger module and their signification.

F A Direction F A Direction Data 0 0 Read 16 0 Write S800 Gate & Delay (delay) 0 1 Read 16 1 Write S800 Gate & Delay (width) 0 2 Read 16 2 Write Secondary Gate & Delay (delay) 0 3 Read 16 3 Write Secondary Gate & Delay (width) 0 4 Read 16 4 Write S800 Delay (delay) 0 5 Read 16 5 Write Coincidence Gate (width) 0 6 Read 16 6 Write Secondary Delay (delay) 0 7 Read 16 7 Write Bypasses (bit pattern) 0 8 Read 16 8 Write S800 Downscaler (factor) 0 9 Read 16 9 Write Secondary Downscaler (factor) 0 10 Read 16 10 Write Trigger Box (bit pattern) 0 11 Read 16 11 Write Go signal (bit) 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) and External Time Stamp Latch (bit 1)

0 14 Read Signature 1 (0x5800) 0 15 Read Signature 2 (0x2367) 1 0 Read 17 0 Write Inspect Channel 1 (wire) 1 1 Read 17 1 Write Inspect Channel 2 (wire) 1 2 Read 17 2 Write Inspect Channel 3 (wire) 1 3 Read 17 3 Write Inspect Channel 4 (wire) 2 0 Read 18 0 Write ADC Gate (width) 2 1 Read 18 1 Write QDC Gate (width) 2 2 Read 18 2 Write TDC Gate (width) 2 3 Read 18 3 Write Coincidence Register Gate (width) 3 0 Read Trigger Box Register (bit pattern) 3 1 Read Time Stamp (bits 0-15) 3 2 Read Time Stamp (bits 16-31) 3 3 Read Time Stamp (bits 32-47) 3 4 Read Time Stamp (bits 48-63)

Inputs and outputs

The following table lists the inputs and outputs to/from the trigger module and their assignment.

Pin Assignment Pin Assignment Pin Assignment Pin Assignment A1 (in) S800 source B1 (out) Raw trigger C1 (in) Busy 1 D1 (out) S800 source A2 (in) Secondary source B2 (out) Live trigger C2 (in) Busy 2 D2 (out) Secondary source A3 (in) External 1 source B3 (out) ADC gate C3 (in) Busy 3 D3 (out) External 1 source A4 (in) External 2 source B4 (out) QDC gate C4 (in) Busy 4 D4 (out) External 2 source A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger A6 (in) Clear module B6 (out) Trigger register gate C6 (in) Busy 6 D6 (out) Coincidence trigger A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger A8 (in) Time stamp clock B8 (out) Live trigger C8 (in) Time stamp latch D8 (out) External 2 trigger

B9 (out)  Inspect 1  C9 (out)  Time stamp clock  D9 (out)  Secondary trigger  
B10 (out)  Inspect 2  C10 (out)  Time stamp latch  D10 (out)  Raw trigger  
B11 (out)  Inspect 3  C11 (out)   D11 (out)  Live trigger  
B12 (out)  Inspect 4  C12 (out)   D12 (out)  Raw pulser  
B13 (out)  Fast clear  C13 (out)   D13 (out)  Live pulser  
B14 (out)   C14 (out)   D14 (out)  Fast clear  
B15 (out)  Go  C15 (out)   D15 (out)  10 Hz  
B16 (out)  Time stamp clock  C16 (out)   D16 (out)  1 Hz  

FPGA firmware

The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications.

File containing the schematics: File:Usbtrig.pdf

Below is the Verilog code used in the configuration for the INTERNAL module: module INTERNAL (N, S1, S2, Clock, F, A, Data_in, DriveRead, Q, X, Data_out, S800Delay, S800Width, SecondaryDelay, SecondaryWidth, S800TimingDelay, CoincTimingWidth, SecondaryTimingDelay, Bypasses, S800Factor, SecondaryFactor, TriggerBox, ADCGate, QDCGate, TDCStart, Coincidence, Inspect1, Inspect2, Inspect3, Inspect4, Register, ClearModule, ClearRegister, Go, TimeStamp, Select, SyncEnable ) ;

input N ; input S1 ; input S2 ; input Clock ; input [4:0] F ; input [3:0] A ; input [23:0] Data_in ; output Q ; output X ; output DriveRead; output [23:0] Data_out ; output [7:0] S800Delay; output [7:0] S800Width ; output [7:0] SecondaryDelay; output [7:0] SecondaryWidth ; output [7:0] S800TimingDelay; output [7:0] CoincTimingWidth ; output [7:0] SecondaryTimingDelay ; output [4:0] Bypasses ; output [9:0] S800Factor ; output [9:0] SecondaryFactor ; output [4:0] TriggerBox ; output [7:0] ADCGate ; output [7:0] QDCGate ; output [7:0] TDCStart ; output [7:0] Coincidence ; output [4:0] Inspect1 ; output [4:0] Inspect2 ; output [4:0] Inspect3 ; output [4:0] Inspect4 ; input [4:0] Register; output ClearModule; output ClearRegister; output Go; input [63:0] TimeStamp; output [1:0] Select; output SyncEnable;

add your declarations here reg X; reg Q; reg DriveRead ; reg ClearModule; reg ClearRegister; reg Go; reg [1:0] Select; reg SyncEnable; reg [23:0] Data_out ; reg [7:0] S800Delay; reg [7:0] S800Width ; reg [7:0] SecondaryDelay; reg [7:0] SecondaryWidth ; reg [7:0] S800TimingDelay; reg [7:0] CoincTimingWidth ; reg [7:0] SecondaryTimingDelay ; reg [4:0] Bypasses ; reg [9:0] S800Factor ; reg [9:0] SecondaryFactor ; reg [4:0] TriggerBox ; reg [7:0] ADCGate ; reg [7:0] QDCGate ; reg [7:0] TDCStart ; reg [7:0] Coincidence ; reg [4:0] Inspect1 ; reg [4:0] Inspect2 ; reg [4:0] Inspect3 ; reg [4:0] Inspect4 ; add your code here always @(posedge Clock) begin

 if (N) begin
 case (F)
   5'd0: begin
   case (A)
     4'd0: Data_out <= {16'd0, S800Delay};
     4'd1: Data_out <= {16'd0, S800Width};
     4'd2: Data_out <= {16'd0, SecondaryDelay};
     4'd3: Data_out <= {16'd0, SecondaryWidth};
     4'd4: Data_out <= {16'd0, S800TimingDelay};
     4'd5: Data_out <= {16'd0, CoincTimingWidth};
     4'd6: Data_out <= {16'd0, SecondaryTimingDelay};
     4'd7: Data_out <= {19'd0, Bypasses};
     4'd8: Data_out <= {14'd0, S800Factor};
     4'd9: Data_out <= {14'd0, SecondaryFactor};
     4'd10: Data_out <= {19'd0, TriggerBox};
     4'd11: Data_out <= {23'd0, Go};
     4'd12: Data_out <= {22'd0, Select};
     4'd13: Data_out <= {23'd0, SyncEnable};
     4'd14: Data_out <= 24'd5800;
     4'd15: Data_out <= 24'd2367;
     default: Data_out <= 24'd0;
   endcase //A
   end // F=0
   
   5'd1: begin
   case (A)
     4'd0: Data_out <= {19'd0, Inspect1};
     4'd1: Data_out <= {19'd0, Inspect2};
     4'd2: Data_out <= {19'd0, Inspect3};
     4'd3: Data_out <= {19'd0, Inspect4};
     default: Data_out <= 24'd0;
   endcase //A
   end // F=1
   
   5'd2: begin
   case (A)
     4'd0: Data_out <= {16'd0, ADCGate};
     4'd1: Data_out <= {16'd0, QDCGate};
     4'd2: Data_out <= {16'd0, TDCStart};
     4'd3: Data_out <= {16'd0, Coincidence};
     default: Data_out <= 24'd0;
   endcase //A
   end // F=2
   
   5'd3: begin
   case (A)
     4'd0: Data_out <= {19'd0, Register};
     4'd1: Data_out <= {8'd0, TimeStamp[15:0]};
     4'd2: Data_out <= {8'd0, TimeStamp[31:16]};
     4'd3: Data_out <= {8'd0, TimeStamp[47:32]};
     4'd4: Data_out <= {8'd0, TimeStamp[63:48]};
     default: Data_out <= 24'd0;
   endcase //A
   end // F=3
   
   5'd9: begin
   end // F=9

5'd16: begin

   if (S1) begin
     case (A)
     4'd0: S800Delay <= Data_in[7:0];
     4'd1: S800Width <= Data_in[7:0];
     4'd2: SecondaryDelay <= Data_in[7:0];
     4'd3: SecondaryWidth <= Data_in[7:0];
     4'd4: S800TimingDelay <= Data_in[7:0];
     4'd5: CoincTimingWidth <= Data_in[7:0];
     4'd6: SecondaryTimingDelay <= Data_in[7:0];
     4'd7: Bypasses <= Data_in[4:0];
     4'd8: S800Factor <= Data_in[9:0];
     4'd9: SecondaryFactor <= Data_in[9:0];
     4'd10: TriggerBox <= Data_in[4:0];
     4'd11: Go <= Data_in[0:0];
     4'd12: Select <= Data_in[1:0];
     4'd13: SyncEnable <= Data_in[0:0];
     endcase //A
   end // S1=1
   end // F=16
     
   5'd17: begin
   if (S1) begin
     case (A)
       4'd0: Inspect1 <= Data_in[4:0];
       4'd1: Inspect2 <= Data_in[4:0];
       4'd2: Inspect3 <= Data_in[4:0];
       4'd3: Inspect4 <= Data_in[4:0];
     endcase //A
   end // S1=1
   end // F=17
     
   5'd18: begin
   if (S1) begin
     case (A)
       4'd0: ADCGate <= Data_in[7:0];
       4'd1: QDCGate <= Data_in[7:0];
       4'd2: TDCStart <= Data_in[7:0];
       4'd3: Coincidence <= Data_in[7:0];
     endcase //A
   end // S1=1
   end // F=18
    
 endcase // F
 end //N=1

end always Clock always @(N or S1 or F or A) begin if (N) begin case (F) 5'd0: begin X = 1'b1; Q = 1'b1; DriveRead = 1'b1; ClearModule = 1'b0; ClearRegister = 1'b0; end F=0

5'd1: begin

   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b1;
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
 end // F=1

5'd2: begin

   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b1;
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
 end // F=2

5'd3: begin

   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b1;
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
 end // F=3

5'd9: begin

   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b0;
   ClearModule = 1'b1;
   ClearRegister = 1'b0;
 end // F=9

5'd10: begin

   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b0;
   ClearModule = 1'b0;
   ClearRegister = 1'b1;
 end // F=9

5'd16: begin

   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b0;
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
 end // F=16
 
 5'd17: begin
   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b0;
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
 end // F=17
 
 5'd18: begin
   X = 1'b1;
   Q = 1'b1;
   DriveRead = 1'b0;
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
 end // F=18
 
 default: begin
   DriveRead = 1'b0; 
   ClearModule = 1'b0;
   ClearRegister = 1'b0;
   X = 1'b0;
   Q = 1'b0;
 end // default F

endcase F end if (N)

 
 else begin
 DriveRead = 1'b0;
 ClearModule = 1'b0;
 ClearRegister = 1'b0;
 X = 1'b0;
 Q = 1'b0;
 end // if (!N)

end always N or S1 or A or F endmodule Technical Development Group home page Wiki main page NSCL NSCL main page Search Toolbox What links here Related changes Special pages Printable version Permanent link Log in This page was last modified on 8 January 2013, at 22:16. This page has been accessed 82 times. Privacy policy About Operations Technical Development Group Wiki Disclaimers Powered by MediaWiki