User Tools

Site Tools


trigger

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
trigger [2014/03/11 11:23]
pereira [Scalers and dead time]
trigger [2017/09/09 17:07] (current)
pereira [Inputs and outputs]
Line 36: Line 36:
 ===== Trigger schematics ===== ===== Trigger schematics =====
    
-The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. ​+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop.
  
 {{:​wiki:​TriggerGUI.png?​900|Trigger schematics of the S800}} {{:​wiki:​TriggerGUI.png?​900|Trigger schematics of the S800}}
Line 56: Line 56:
  
 ==== Inspect channels ==== ==== Inspect channels ====
-A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. ​+A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI by right clicking on the corresponding drawn "​wire"​, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. ​
  
  
Line 77: Line 77:
  
 ==== Inputs and outputs ==== ==== Inputs and outputs ====
-A table with the list of inputs/​outputs channels to/from the trigger module and their assignment ​can be found [[Inputs and outputs | here]].+The list of inputs/​outputs channels to/from the ULM trigger moduleand their assignment, is shown in the bale below:
  
 +^ Pin     ^ Assignment ​       ^ Pin       ^ Assignment ​           ^ Pin       ^ Assignment ​      ^ Pin       ^ Assignment |
 +^ A1 (in) | S800 source ​      ^ B1 (out)  | Raw trigger ​          ^ C1 (in)   | Busy 1           ^ D1 (out)  | S800 source |
 +^ A2 (in) | Secondary source ​ ^ B2 (out)  | Live trigger ​         ^ C2 (in)   | Busy 2           ^ D2 (out)  | Secondary source |
 +^ A3 (in) | External 1 source ^ B3 (out)  | ADC gate              ^ C3 (in)   | Busy 3           ^ D3 (out)  | External 1 source |
 +^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source |
 +^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger |
 +^ A6 (in) | Clear module ​     ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6   ^ D6 (out)  | Coincidence trigger |
 +^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger |
 +^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger ​         ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger|
 +^         ​| ​                  ^ B9 (out)  | Inspect 1             ^ C9 (out)  | Time stamp clock ^ D9 (out)  | Secondary trigger |
 +^         ​| ​                  ^ B10 (out) | Inspect 2             ^ C10 (out) | Time stamp latch ^ D10 (out) | Raw trigger |
 +^         ​| ​                  ^ B11 (out) | Inspect 3             ^ C11 (out) |                  ^ D11 (out) | Live trigger |
 +^         ​| ​                  ^ B12 (out) | Inspect 4             ^ C12 (out) |                  ^ D12 (out) | Raw pulser |
 +^         ​| ​                  ^ B13 (out) | Fast clear            ^ C13 (out) |                  ^ D13 (out) | Live pulser |
 +^         ​| ​                  ^ B14 (out) |                       ^ C14 (out) |                  ^ D14 (out) | Fast clear |
 +^         ​| ​                  ^ B15 (out) | Go                    ^ C15 (out) |                  ^ D15 (out) | 10 Hz |
 +^         ​| ​                  ^ B16 (out) | Time stamp clock      ^ C16 (out) |                  ^ D16 (out) | 1 Hz |
 ==== FPGA firmware ==== ==== FPGA firmware ====
 The firmware of the trigger module is shown in the following files. The {{:​wiki:​Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications. The firmware of the trigger module is shown in the following files. The {{:​wiki:​Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications.
Line 84: Line 101:
  
 ====== Time stamping ====== ====== Time stamping ======
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#​Trigger Schematics|GUI]]). The clock is inhibited by a "​Go"​ signal controlled by the trigger module. While "​Go"​ is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "​[[Trigger#​Begin sequence|Begin sequence]]"​). The clock signal is released when the "​Go"​ signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. ​+The S800 ULM trigger ​module ​provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used (as it is donefor instance, when running with GRETINA). The clock is inhibited by a "​Go"​ signal controlled by the trigger module. While "​Go"​ is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "​[[Trigger#​Begin sequence|Begin sequence]]"​). The clock signal is released when the "​Go"​ signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. ​
  
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crateor in other data acquisition systems coupled to the S800.  +The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:​wiki:​stamp64.pdf|here}}. The inputs are the following: ​
- +
- +
-The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:​wiki:​stamp64.pdf|here}}. The inputs are the following: ​+
  
  
Line 107: Line 121:
  
 ====== Configuration for S800 in tandem with other detectors ====== ====== Configuration for S800 in tandem with other detectors ======
-In its standard configuration,​ the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module. ​+In its standard configuration,​ the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 ([[Trigger#​Inputs and outputs|inputs C1 and C2]]) of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module. ​
 To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: ​ To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: ​
  
Line 142: Line 156:
  
 ====== Begin sequence ====== ====== Begin sequence ======
 +OBSOLETE: THIS SECTION IS BEING UPDATED
 +
 The internal "​Go"​ state of the trigger module is controlled via CAMAC commands. When "​Go"​ is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "​Go"​ state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. The internal "​Go"​ state of the trigger module is controlled via CAMAC commands. When "​Go"​ is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "​Go"​ state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
  
Line 153: Line 169:
  
 ====== Scalers and dead time ====== ====== Scalers and dead time ======
-The "​D"​ connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping of the inputs and outputs of the trigger module in section [[Trigger#​Inputs and outputs|Inputs and outputs]]). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, ​in addition to the information coded for each event in the trigger register.  +The "​D"​ connector of the trigger module is directly connected to first 16 inputs of a {{:​wiki:​Manual_LeCroy_Scaler_4434.pdf|32-channel ​scaler ​LeCroy 4434 module}} (see mapping of the inputs and outputs of the trigger module in section [[Trigger#​Inputs and outputs|Inputs and outputs]]). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, ​besides ​the information coded for each event in the trigger register. ​
- +
-In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.  +
- +
-The remining 16 scaler input channels (pins 17 to 32 in module) are connected to a **16-channel CFD CAEN C808**, which sends the signals from the S800 detectors (**E1 up,** **E1 down**, **CRDC1**, **CRDC2**, **OBJ_SCI**,​ **A1900 SCI**, and **OR Hodoscope**).  +
- +
-The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout.  +
- +
- +
-^ Channel name ^ Channel number ^ Channel name ^ Channel number | +
-| Live.Trigger ​ ^ 10 | Raw.Trigger ​   ^ 9 | +
-| Live.Clock ​   ^ 12 | Raw.Clock ​     ^ 11 | +
-| S800.Source ​  ^ 0 | S800.Trigger ​  ^ 4 | +
-| Second.Source ^ 1 | Second.Trigger ^ 8 | +
-| Ext1.Source ​  ^ 2 | Ext1.Trigger ​  ^ 6 | +
-| Ext2.Source ​  ^ 3 | Ext2.Trigger ​  ^ 7 |  +
-| Coinc.Trigger ^ 5 |                ^  | +
-| E1.Up         ^ 16 | E1.Down ​       ^ 17 | +
-| E2.Up         ^ 18 | E2.Down ​       ^ 19 | +
-| CRDC1.Anode ​  ^ 22 | CRDC2.Anode ​   ^ 23 | +
-| TPPAC1 ​       ^ 27 | TPPAC2 ​        ^ 28 | +
-| OBJ.Scint ​    ^ 24 | XFP.Scint ​     ^ 25 | +
-| TAR.Scint ​    ^ 26 | XFP.Scint ​     ^ 25 | +
-| S800.Source ​  ^ 0 | OBJ.Si ​        ^ 26 | +
-| S800.Source ​  ^ 0 | OBJ.Scint ​     ^ 24 | +
-| S800.Source ​  ^ 0 | XFP.Scint ​     ^ 25 | +
-| Hodo.OR ​      ^ 30 |                ^  |  +
- +
-In principle, it is possible to include other signals into the scaler channels that are not used. This requires changes in some of the tcl scripts. Make sure that you communicate with the S800 responsible,​ and of course, do not do anything if you don't know what you are doing. The list below describes the steps that need to be followed to include new channels in the scaler. +
- +
-  * Modify the scaler display script to include the new signals: Go to **/​user/​s800/​Documents/​Run/​scalers/​USBDAQ** and edit file **s800scl.des** to include the new channels (make sure that you make a copy of the old file so that it can be recovered when the new signals are not needed anymore). Save the new file. +
- +
-  * Connect the new logic signals into the free input channels of the 1**6-ch CFD CAEN C808.** Follow the output ribbon cable to know the corresponding scaler channel where the new signals from the CFD are sent. +
- +
-  * Enable the new CFD CAEN C808 channels (if they are not yet enabled): Go to **/​user/​s800/​operations/​daq/​usb/​Scripts** and edit file C**C0105Begin.tcl**. There ist an array variable **cfd EnableOnlyChannels** that includes the list of enabled channels. Make sure that the new channels are included. Save the new file.+
  
-  * Start the scalers ​display scriptYou should see the new channels in the display counting. If they are zero, the CFD thresholds may be too high. If that is the case, you should lower them in file **s800cfdini.tcl** (directory **/​user/​s800/​operations/​daq/​usb/​Configs**).+For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. ​This is the preferred method because ​the pulser ​is not subject to possible double triggering effects like the raw trigger
  
 +The remining 16 scaler input channels (pins 17 to 32 in module) are connected to an ECL-NIM-ECL converter fed by a 16-channel {{:​wiki:​MCFD-16.pdf|Mesytec CFD (MCFD-16)}},​ which sends the signals from the S800 detectors (**E1 up,** **E1 down**, **CRDC1**, **CRDC2**, **OBJ_SCI**,​ **A1900 SCI**, and **OR Hodoscope**). ​
  
 +The complete list of scaler channels can be found [[Scaler Channel Description|here]].
  
  
  
trigger.1394551424.txt.gz · Last modified: 2014/03/11 11:23 by pereira